Both processes and new tools to go with them use electrical current to locally control the deposition of copper, in plating steps, and the removal of metal, in polishing sequences, across wafers with diameters of 200 or 300 mm, said ACM managers at a press conference at Semicon Southwest in Austin. The novel electropolishing process and tool is capable of removing materials at the atomic layer down to 80 angstroms, said David Wang, co-founder and chief executive officer of ACM of Fremont, Calif.

"Electropolishing has been around for hundreds of years, and it is a finishing technology used in other industries, such as automotive," Wang said. "However, we have a new concept to apply it to wafer processing."

The development of electropolishing techniques for planarization in dual damascene copper processes opens up a range of choices for low-k dielectric materials because insulating films do not have to withstand the stress of chemical mechanical planarization (CMP), Wang said. As a result, softer dielectric films--such as spin-on, porous Xerogel materials--become viable candidates for integration in damascene processes with copper. These porous films can be "tunable" and have low-k dielectric ratings less than 1.8 vs. above 3 for many of the current low-k insulators being used in prototype copper processes.

The ability to hold up under the stress and strain of chemical mechanical polishing has been a major factor in selecting a low-k dielectric insulator for copper interconnects. Often, insulating materials with lower dielectric constant ratings are not able to meet the mechanical-strength requirements for CMP, which is used to flatten layers in interconnects and remove excess amounts of copper from vias and trenches.

Other companies are also pursuing alternatives to CMP. Last year, for example, SEZ Group of Villach, Austria, and Honeywell Inc.'s Electronics Materials Division formed an alliance to develop a wet-chemical planarization technique for chip processing (see Aug. 24, 1999, story). Under the partnership, the two companies are aiming to eliminate mechanically-induced damage caused by CMP in porous low-k materials.

ACM's Wang said his company's approach is different than the one pursued by SEZ. "That technology is a wet-chemical process, which will be difficult to control as feature sizes shrink," he said. But the goal of replacing CMP is similar.

"Low-k dielectrics are available, but the problem is they are not strong enough to stand up to CMP," he said. "Our electropolishing system is 'stress free polishing,'" Wang added.

If the concept catches on, it could threaten a huge wafer tool segment that promises to reach $1.2 billion in revenues for copper processing by 2003, according to a market forecast by VLSI Research Inc. "There may not be a need for copper CMP," Wang suggested.

Two-year-old ACM believes its patented concepts will also extend the use of copper electroplating to the 0.035-micron technology node, which is expected to be used by chip makers nearly a dozen years from now based on industry roadmaps. In this electroplating process, current is used to control the deposition of copper-fill in plating steps with seed layers between 500 and 50 angstroms.

ACM Research has been developing the copper electroplating and electropolishing technologies for the past 34 months. Wang said ACM is now discussing potential technology licenses with a range of companies, including equipment suppliers and semiconductor manufacturers. "We want to make this technology mainstream two to three years from now," he added.

The company said it has created a unique design of stacked chambers with independent robotics to team up the plating and polishing systems. They can be used separately with other deposition and planarization systems. ACM has created a beta tool for both the electroplating and electropolishing technologies.

The Ultra ECP electroplating system has a throughput of 60 wafers per hour using multiple stacked chambers. ACM's Ultra SFP (stress free polishing) system uses three polishing chambers and three cleaning chambers. It will remove a minimum thickness of 50 angstroms and etch away at a rate of 0.1 to 0.5 microns per minute to achieve a throughput of 60 wafers per hour for 1.0-micron films, said the company. The cost of Ultra SFP will be less than $2 per wafer vs. $4-to-5 with CMP tools, Wang said.