PHOENIX--National Scientific Corp. here reported it has received a U.S. patent for a high-speed, low-power memory design--called a TunnelMOS memory--which the company says is faster and denser than conventional CMOS static RAMs.
The TunnelMOS memory design eliminates the need for P-channel transistors in the memory cell, said the company. The new design requires two more mask steps than conventional CMOS SRAMs, but it its read access times are 30% faster and writing cycles are 50% faster than static RAM cells, according to National Scientific.
Costs can be saved because the TunnelMOS cell size is 30% smaller than conventional SRAM cells, said the Phoenix company, which licenses technology to chip manufacturers.
According to the company, the TunnelMOS memory is fully compatible with existing CMOS process technology. However, the new design improves upon CMOS static RAMs by eliminating the use of P-channel transistors, which are slower and larger than N-channel transistors, said the company.
National Scientific claims its SRAM memory cell outperforms the standard CMOS static RAM cells because it is based on an innovative architecture, which combines faster N-channel transistors with tunnel diode technology to replace the P transistors.
In addition to being faster and smaller, the TunnelMOS memory cell consumes 45% less active power than conventional CMOS static RAM designs, said National Scientific. The static noise margin of the TunnelMOS cell is the same as conventional CMOS SRAMs, said the company, whose stock is publicly traded in the U.S. over the counter.
